The present invention relates to sampled signal detection systems and, more particularly, to such systems used in information storage systems.
In information storage systems such as digital magnetic recording systems, data is recorded in a moving magnetic media layer by a storage, or "write", electrical current-to-magnetic field transductor, or "head", positioned immediately adjacent thereto. The data is stored or written to the magnetic media by switching the directions of flow of a substantially constant magnitude write current provided through windings in the storage transducer. Each such write current transition to an opposite direction flow results in a corresponding reversal of the magnetization direction, in that portion of the magnetic media just passing by the transducer during the changing of the current direction, with respect to the magnetization direction in that media induced by the previous current flow in the opposite direction. In one coding scheme, often termed "nonreturn-to-zero inverted (NRZI), each magnetization direction reversal over a portion of the media moving past the transducer represents a binary digit "1" and the lack of any such reversal in that portion represented a binary digit "0".
When data so stored is to be subsequentially recovered, a retrieval, or "read" magnetic field-to-voltage transducer (which may be the same as the storage transducer if both rely on inductive coupling between the media fields and the transducer), or "head", is positioned to have the magnetic media, containing the previously stored data, pass thereby. Such passing by of the media adjacent to the transducer permits the flux accompanying the magnetization reversal regions in that media to induce a corresponding voltage pulse in forming an output analog read signal for that retrieval transducer or, alternatively, permits the flux accompanying these magnetization reversal regions to, in turn, change a transducer circuit parameter to thereby provide such an output signal voltage pulse. In the coding scheme described above, each such voltage pulse in the read transducer output signal due to the reversal of magnetization directions between adjacent media portions passing the transducer represents a binary digit "1", and the absence of a pulse in correspondence with such portions represents a binary digit "0".
Digit data magnetic recording systems have used peak detection methods for the detection of such voltage pulses in the retrieved analog signal as the basis for digitizing this signal. Such methods are based on determining which peaks in that signal exceed a selected threshold to determine that a binary digit "1" related pulse occurred in the retrieved signal, and also use the times between those voltage pulses to reconstruct the timing information used in the preceding recording operation in which the data were stored in the magnetic media as described above. The analog retrieved signal is provided to a phase-locked loop forming a controlled oscillator, or a phase-lock oscillator or synchronizer, which produces an output timing signal, or "clock" signal, from the positions of the detected peaks in this analog retrieved signal. Absolute time is not used in operating the data retrieval system portion since the speed of the magnetic media varies over time during both the storage operation and the retrieval operation to result in nonuniform time intervals, or nonuniform multiples thereof, occurring between the voltage pulses in the analog retrieved signal.
In more recent digital data magnetic recording systems, partial response signaling is used which involves the acceptance of a predetermined degree of intersymbol interference occurring between the recovered data pulses involved in forming the transducer analog output signal which pulses again represent data symbols obtained from the recorded binary data. Such an arrangement allows for an increased density of data being stored in the magnetic media. Data recovery proceeds by periodically sampling the amplitude of this analog retrieved signal as the basis for digitizing this signal, the taking of such samples being initiated by pulses in the clocking signal supplied by a phase-lock oscillator. The magnitudes of the samples initiated by this clocking signal have magnitude contributions to them by more than one pulse representing a retrieved binary digit because of the planned intersymbol interference.
As part of providing a signal transmission channel with frequency response characteristics suitable for partial response signaling, digital magnetic recording systems often choose a type of partial response signaling system termed a class 4 system. Such a system is particularly suitable for magnetic recording in view of the nature of the spectrum of the resulting analog retrieved signal because the signal channel requires relatively little equalization by the equalizer used therewith to provide a channel frequency characteristic substantially matching the class 4 system signal spectrum. In such a class 4 partial response signaling system, the magnitudes of the retrieved signal waveform after equalization at any sampling instant has a contribution thereto from the magnitude of that pulse, representing a corresponding recorded binary digit, newly included in the analog retrieved signal near that instant, if any, but not from the immediately preceding pulse one sampling clock period earlier. There will, however, be a further contribution from the magnitude of the next earlier occurring pulse, if any, in the signal waveform two sampling clock periods but not from others occurring even earlier. As a result, samples of the analog retrieved waveform can be divided into two interleaved subsequences with one containing the even numbered samples and the other containing the odd numbered samples. Each such subsequence can be submitted independently to a Viterbi detector as part of a maximum likelihood symbol detection arrangement.
Here, too, the analog retrieved signal in such a partial response signaling system is provided to a phase-lock oscillator as the basis for recovering the clocking signal reflected in the timing represented by the occurrences of pulses representing digital data in the analog retrieved signal, i.e. the analog read signal from the transducer. Accurate recovery of the binary information in this signal requires accuracy in the times of taking samples of that signal, and in the corresponding synchronization of the operation of the rest of the detection system therewith. One requirement for successfully recovering this timing information is that there not be too many "0" bit symbols in a row in the binary data which would lead to too few pulses occurring in the analog read signal forming the basis from which the phase-lock oscillator derives such timing information. This need is satisfied by properly precoding the data provided for recording on the magnetic disk media using a code having a nature that results in preventing any such inordinately log sequences of "0" data bits.
The average frequency of the phase-lock oscillator representing the derived timing of the occurrence of pulses representing binary data in the analog read signal must clearly equal the average frequency of the occurrence of pulses in that read signal since the read detection system must generate as many data bits, based on the frequency of sampling, as were actually recorded. However, even having met this requirement, the phase-lock oscillator output clocking signal will exhibit phase variation representing variations in just where each pulse in the analog read signal is sampled over its duration. This variation in the timing phase is usually referred to as phase jitter or timing jitter. Such jitter must be controlled in the clocking signal of the phase-lock oscillator to achieve accurate sampling.
The analog read signal, x(t), as provided by the read transducer, is initially subjected to analog signal processing operations including amplification and equalization. The resulting processed analog read signal, y(t), after such analog processing, is then read for sampling, and will be sampled at times which can be represented as (kT+.tau.[k]). The period of the clocking signal, i.e. the sampling interval, is designated T so that the time to the current period is kT where k is an appropriate integer giving the number of sampling intervals which have occurred since the initial interval, and the phase error .tau.[k] represents the timing error in the k.sup.th sampling interval. Thus, the sample currently taken has a magnitude value of y(kT+.tau.[k]). That is, at sample time (kT+.tau.[k]), the phase-lock oscillator output clock signal causes a sample-and-hold circuit to hold the then current value of y(t) to create an analog sample value of y(kT+.tau.[k]), or sample[i], which is then sent to an analog-to-digital converter for conversion into an equivalent digital value.
In a partial response system absent noise in the channel, the output of the equalizer y(t) ideally is one of three sample values, +1, 0 or -1, obtained at the beginning of each sampling period. However, because of asymmetries and scaling effects occurring in the partial response signal transmission system channel, the actual voltage values obtained in noiseless samples will be found instead to be V.sub.s+, 0, and V.sub.g- in correspondence with these ideal sample just set out above to provide the actually used system ideal sample values, ideal[i], representing the value of the i.sup.th ideal sample without providing the specific time dependence. The values for V.sub.s+ and V.sub.g- can be obtained from an averaging arrangement for finding average values for high and low value samples.
Because of noise, timing jitter, and other signal transmission defects, the sample value measured at a sampling period sample [i] will not usually be equal to one of the ideal sample values ideal[i]. Thus, there will instead be an error having a value equal to EQU error[i]=sample[i]-ideal[i].
This error has been controlled in the past with respect timing jitter contributions by adaptively adjusting the timing phase in a feedback loop using in that loop an unbiased, minimum variance estimator for the desired loop timing function of EQU z=sample[i].multidot.ideal[i-1]+sample[i-1].multidot.ideal[i]
to establish the nature of the loop as EQU .tau.[i+1=.tau.[i]-cz[i]
to provide recursive timing phase corrections. Such a system is shown in FIG. 1.
In the system of FIG. 1, a magnetic material covered disk, 10, containing pluralities of magnetization direction reversals along each of a plurality of more or less concentric, circular tracks is rotated past a data retrieval transducer arrangement, 11, or "read head", positioned adjacent a selected track by a "head" positioner and initial signal processor, 12, about a spindle, 13, to provide an initial analog read signal x(t). This signal is subjected to further processing in a variable gain amplifier, 14, and subsequently in a linear channel equalizer, 15.
Equalizer 15 has, beginning from its input, a succession of delay elements, 16, to form a delay line with each of element 16 providing a delay of T seconds, nominally equal to the sampling interval, to input signals provided thereto by passing those input signals through a cascade of three T/3 delay filters therein. Thus, x(t) is presented to the input of equalizer 15 to be introduced into this delay line with successive versions thereof delayed by T seconds being tapped from this delay line and provided to corresponding ones of a plurality of tap weight multipliers, 17, to be multiplied by the associated tap weight value, w.sub.n. The weighted values form multipliers 17 are summed in summers, 18, to provide the analog output y(t) of equalizer 15. Changes in the tap weights are provided from a plurality of corresponding weighting change multipliers, 19, based on multiplying the corresponding delayed version of the input signal x(t) by a scaled version of an error signal determined from samples taken of the output signal y(t) in a sampler, 20, based on a sample and hold circuit. These samples are supplied to an error determiner, 21, along with the scaled ideal values for such samples from a source thereof, 22, from which determiner 21 determines the error which is passed through a magnitude scaler, 23, to weighting change multipliers 19.
The samples obtained in sampler 20 and the scaled ideal sample values are also supplied to corresponding T second delay elements, 24 and 25, respectively, and directly to a phase detector, 26, to which the delayed versions from delay elements 24 and 25 are also supplied. Phase detector 26 uses these inputs to form the estimate described above which is scaled by a step size multiplier, 27, and then used to control a voltage-controlled oscillator that provides the sampling clock signal to sampler 20 to initiate the taking of each sample of y(t) and to synchronize other actions in the signal processing system.
Although this provides a useable timing error correction arrangement, the timing errors are not corrected as well as possible in those situations in which there are successive samples with values of zero. In this situation, the estimator z can be seen to being subject to taking a value of zero on such occasions so that no timing error corrections will be provided on such occasions. Thus, there is desired a timing error correction arrangement providing better timing error correction without a significant increase in complexity.